Extraction of geometry-related interconnect variation based on parasitic capacitance data
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سال
: 2014شناسه الکترونیک: 10.1109/LED.2014.2344173
کلیدواژه(گان): capacitance measurement,charge-coupled devices,geometry,integrated circuit interconnections,integrated circuit testing,signal generators,ITF,charge-induced-injection error-free charge-based capacitance measurement,geometry-related interconnect variation extraction flow,interconnect parasitic extraction,interconnect technology file,layout parasitic extraction tool,nonoverlapping signal generation circuitry,on-chip interconnect test technique,parasitic capacitance data,size 55 nm,D
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آمار بازدید
Extraction of geometry-related interconnect variation based on parasitic capacitance data
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| contributor author | Li-Jie Sun | |
| contributor author | Jia Cheng | |
| contributor author | Zheng Ren | |
| contributor author | Gan-Bing Shang | |
| contributor author | Shao-Jian Hu | |
| contributor author | Shou-Mian Chen | |
| contributor author | Yu-Hang Zhao | |
| contributor author | Long Zhang | |
| contributor author | Xiao-Jin Li | |
| contributor author | Yan-Ling Shi | |
| date accessioned | 2020-03-13T00:18:40Z | |
| date available | 2020-03-13T00:18:40Z | |
| date issued | 2014 | |
| identifier issn | 0741-3106 | |
| identifier other | 6879252.pdf | |
| identifier uri | http://libsearch.um.ac.ir:80/fum/handle/fum/1142018 | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | Extraction of geometry-related interconnect variation based on parasitic capacitance data | |
| type | Journal Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8324499 | |
| subject keywords | capacitance measurement | |
| subject keywords | charge-coupled devices | |
| subject keywords | geometry | |
| subject keywords | integrated circuit interconnections | |
| subject keywords | integrated circuit testing | |
| subject keywords | signal generators | |
| subject keywords | ITF | |
| subject keywords | charge-induced-injection error-free charge-based capacitance measurement | |
| subject keywords | geometry-related interconnect variation extraction flow | |
| subject keywords | interconnect parasitic extraction | |
| subject keywords | interconnect technology file | |
| subject keywords | layout parasitic extraction tool | |
| subject keywords | nonoverlapping signal generation circuitry | |
| subject keywords | on-chip interconnect test technique | |
| subject keywords | parasitic capacitance data | |
| subject keywords | size 55 nm | |
| subject keywords | D | |
| identifier doi | 10.1109/LED.2014.2344173 | |
| journal title | Electron Device Letters, IEEE | |
| journal volume | 35 | |
| journal issue | 10 | |
| filesize | 926778 | |
| citations | 0 |