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Innovative Scaling Method to Minimize Cost of Integrated Circuit Packages and Devices

contributor authorBhattacharyya, Bidyut K.
contributor authorLaskar, Nivedita
contributor authorDebnath, Shoubhik
contributor authorBaral, Debasis
date accessioned2020-03-13T00:17:42Z
date available2020-03-13T00:17:42Z
date issued2014
identifier issn2156-3950
identifier other6874514.pdf
identifier urihttp://libsearch.um.ac.ir:80/fum/handle/fum/1141432?show=full
formatgeneral
languageEnglish
publisherIEEE
titleInnovative Scaling Method to Minimize Cost of Integrated Circuit Packages and Devices
typeJournal Paper
contenttypeMetadata Only
identifier padid8323869
subject keywordscost reduction
subject keywordsintegrated circuit noise
subject keywordsintegrated circuit packaging
subject keywordsIC chip
subject keywordsIC products
subject keywordscost minimization
subject keywordsdie design methodology
subject keywordsinductive noise
subject keywordsinnovative scaling method
subject keywordsintegrated circuit packages
subject keywordsoptimum package solutions
subject keywordspower delivery solutions
subject keywordsCapacitance
subject keywordsClocks
subject keywordsInductance
subject keywordsNoise
subject keywordsPower supplies
subject keywordsResistance
subject keywordsSilicon
subject keywords(L) , (C) , and (R) of packages
subject keywordsDie decoupling capacitance
subject keywordsL, C, and R of packages
subject keywordsdie decoupling resistance
subject keywordsorganic land grid array core/coreless packages
identifier doi10.1109/TCPMT.2014.2339272
journal titleComponents, Packaging and Manufacturing Technology, IEEE Transactions on
journal volume4
journal issue9
filesize1815189
citations0


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