High-Throughput Turbo Decoder With Parallel Architecture for LTE Wireless Communication Standards
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: 2014DOI: 10.1109/TCSI.2014.2332266
Keyword(s): 3G mobile communication,CMOS integrated circuits,Long Term Evolution,VLSI,integrated circuit design,maximum likelihood decoding,telecommunication standards,turbo codes,3GPP-LTE standard,90 nm CMOS technology,ACSU,LBCJR algorithm,LTE wireless communication standards,LTE-Advanced standard,VLSI design aspect,add-compare-select-unit,backward state metric computation,critical path delay reduction,high-speed maximum a posteriori probability decoders,high-throughput turbo decoder,it
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High-Throughput Turbo Decoder With Parallel Architecture for LTE Wireless Communication Standards
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| contributor author | Shrestha, Ranjay | |
| contributor author | Paily, Roy P. | |
| date accessioned | 2020-03-13T00:12:02Z | |
| date available | 2020-03-13T00:12:02Z | |
| date issued | 2014 | |
| identifier issn | 1549-8328 | |
| identifier other | 6847747.pdf | |
| identifier uri | http://libsearch.um.ac.ir:80/fum/handle/fum/1137978 | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | High-Throughput Turbo Decoder With Parallel Architecture for LTE Wireless Communication Standards | |
| type | Journal Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8319970 | |
| subject keywords | 3G mobile communication | |
| subject keywords | CMOS integrated circuits | |
| subject keywords | Long Term Evolution | |
| subject keywords | VLSI | |
| subject keywords | integrated circuit design | |
| subject keywords | maximum likelihood decoding | |
| subject keywords | telecommunication standards | |
| subject keywords | turbo codes | |
| subject keywords | 3GPP-LTE standard | |
| subject keywords | 90 nm CMOS technology | |
| subject keywords | ACSU | |
| subject keywords | LBCJR algorithm | |
| subject keywords | LTE wireless communication standards | |
| subject keywords | LTE-Advanced standard | |
| subject keywords | VLSI design aspect | |
| subject keywords | add-compare-select-unit | |
| subject keywords | backward state metric computation | |
| subject keywords | critical path delay reduction | |
| subject keywords | high-speed maximum a posteriori probability decoders | |
| subject keywords | high-throughput turbo decoder | |
| subject keywords | it | |
| identifier doi | 10.1109/TCSI.2014.2332266 | |
| journal title | Circuits and Systems I: Regular Papers, IEEE Transactions on | |
| journal volume | 61 | |
| journal issue | 9 | |
| filesize | 3155839 | |
| citations | 0 |