Spike Anneal Peak Temperature Impact on 1T-DRAM Retention Time
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سال
: 2014شناسه الکترونیک: 10.1109/LED.2014.2319094
کلیدواژه(گان): DRAM chips,annealing,silicon-on-insulator,1T-DRAM retention time,SOI,drain electrical field,drain implantation,dynamic random access memory cells,single silicon-on-insulator transistor,source implantation,spike anneal peak temperature,temperature 1070 degC to 1050 degC,temperature 20 degC,tunneling current,Annealing,Logic gates,Mathematical model,Random access memory,Time measurement,Transistors,Tunneling,1T-DRAM,1T-DRAM.,Capacitorless DRAM,SOI
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Spike Anneal Peak Temperature Impact on 1T-DRAM Retention Time
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| contributor author | Nissimoff, Albert | |
| contributor author | Martino, Joao Antonio | |
| contributor author | Aoulaiche, Marc | |
| contributor author | Veloso, A. | |
| contributor author | Witters, Liesbeth Johanna | |
| contributor author | Simoen, Eddy | |
| contributor author | Claeys, Cor | |
| date accessioned | 2020-03-13T00:02:25Z | |
| date available | 2020-03-13T00:02:25Z | |
| date issued | 2014 | |
| identifier issn | 0741-3106 | |
| identifier other | 6811203.pdf | |
| identifier uri | http://libsearch.um.ac.ir:80/fum/handle/fum/1132227 | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | Spike Anneal Peak Temperature Impact on 1T-DRAM Retention Time | |
| type | Journal Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8313173 | |
| subject keywords | DRAM chips | |
| subject keywords | annealing | |
| subject keywords | silicon-on-insulator | |
| subject keywords | 1T-DRAM retention time | |
| subject keywords | SOI | |
| subject keywords | drain electrical field | |
| subject keywords | drain implantation | |
| subject keywords | dynamic random access memory cells | |
| subject keywords | single silicon-on-insulator transistor | |
| subject keywords | source implantation | |
| subject keywords | spike anneal peak temperature | |
| subject keywords | temperature 1070 degC to 1050 degC | |
| subject keywords | temperature 20 degC | |
| subject keywords | tunneling current | |
| subject keywords | Annealing | |
| subject keywords | Logic gates | |
| subject keywords | Mathematical model | |
| subject keywords | Random access memory | |
| subject keywords | Time measurement | |
| subject keywords | Transistors | |
| subject keywords | Tunneling | |
| subject keywords | 1T-DRAM | |
| subject keywords | 1T-DRAM. | |
| subject keywords | Capacitorless DRAM | |
| subject keywords | SOI | |
| identifier doi | 10.1109/LED.2014.2319094 | |
| journal title | Electron Device Letters, IEEE | |
| journal volume | 35 | |
| journal issue | 6 | |
| filesize | 703462 | |
| citations | 0 |