Show simple item record

High speed integer multiplier designs for reconfigurable systems

contributor authorAnjana, S.
contributor authorPradeep, C.
date accessioned2020-03-12T22:06:05Z
date available2020-03-12T22:06:05Z
date issued2014
identifier other6992993.pdf
identifier urihttp://libsearch.um.ac.ir:80/fum/handle/fum/1071433?locale-attribute=en&show=full
formatgeneral
languageEnglish
publisherIEEE
titleHigh speed integer multiplier designs for reconfigurable systems
typeConference Paper
contenttypeMetadata Only
identifier padid8207505
subject keywordsdata flow graphs
subject keywordsn reconfigurable architectures
subject keywordsn scheduling
subject keywordsn CGRA
subject keywordsn application mapping
subject keywordsn automated synthesis flow
subject keywordsn backward simultaneous scheduling-binding
subject keywordsn backward traversal
subject keywordsn coarse grained reconfigurable architecture
subject keywordsn compilation
subject keywordsn digital signal domain
subject keywordsn dynamic graph transformations
subject keywordsn formal model
subject keywordsn image processing domain
subject keywordsn Dynamic scheduling
subject keywordsn Reconfigurable architectures
subject keywordsn Registers
subject keywordsn Routing
subject keywordsn Space exploration
subject keywordsn Binding
identifier doi10.1109/ASAP.2014.6868652
journal titleontrol, Instrumentation, Communication and Computational Technologies (ICCICCT), 2014 International
filesize806581
citations0


Files in this item

FilesSizeFormatView

There are no files associated with this item.

This item appears in the following Collection(s)

Show simple item record