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FPGA implementation of IEEE-754 floating point Karatsuba multiplier

contributor authorKodali, R.K.
contributor authorGundabathula, S.K.
contributor authorBoppana, L.
date accessioned2020-03-12T22:06:03Z
date available2020-03-12T22:06:03Z
date issued2014
identifier other6992974.pdf
identifier urihttp://libsearch.um.ac.ir:80/fum/handle/fum/1071414?locale-attribute=fa&show=full
formatgeneral
languageEnglish
publisherIEEE
titleFPGA implementation of IEEE-754 floating point Karatsuba multiplier
typeConference Paper
contenttypeMetadata Only
identifier padid8207486
subject keywordsNewton-Raphson method
subject keywordsn floating point arithmetic
subject keywordsn FP operations
subject keywordsn FP representation precision
subject keywordsn adapted Newton-Raphson iteration
subject keywordsn double-precision
subject keywordsn error analysis
subject keywordsn floating point expansion reciprocal
subject keywordsn multiple component format
subject keywordsn multiple-precision libraries
subject keywordsn numerical problems
subject keywordsn relative error bound
subject keywordsn single-precision
subject keywordsn standard machine precision FP numbers
subject keywordsn truncated addition operation
subject keywordsn truncated multiplication operation
subject keywordsn Algorithm desig
identifier doi10.1109/ASAP.2014.6868632
journal titleontrol, Instrumentation, Communication and Computational Technologies (ICCICCT), 2014 International
filesize1087860
citations0


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