Probabilistic model checking based DAL analysis to optimize a combined TMR-blind-scrubbing mitigation technique for FPGA-based aerospace applications
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سال
: 2014شناسه الکترونیک: 10.1109/ICEP.2014.6826723
کلیدواژه(گان): assembling,n moulding,n three-dimensional integrated circuits,n wafer level packaging,n 3D IC assembly process,n CoW technology,n SMC,n WLP,n chip thickness,n chip-on-wafer technology,n sheet-type molding compound,n three-dimensional integrated circuit technology,n ultra-thin chip stacking technology,n wafer-level-packaging,n Assembly,n Bonding,n Semiconductor device measurement,n Silicon,n Strain,n Through-silicon vias,n chip-on-wafer
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Probabilistic model checking based DAL analysis to optimize a combined TMR-blind-scrubbing mitigation technique for FPGA-based aerospace applications
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| contributor author | Hoque, K.A. | |
| contributor author | Mohamed, O.A. | |
| contributor author | Savaria, Y. | |
| contributor author | Thibeault, C. | |
| date accessioned | 2020-03-12T21:51:41Z | |
| date available | 2020-03-12T21:51:41Z | |
| date issued | 2014 | |
| identifier other | 6961856.pdf | |
| identifier uri | http://libsearch.um.ac.ir:80/fum/handle/fum/1063108 | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | Probabilistic model checking based DAL analysis to optimize a combined TMR-blind-scrubbing mitigation technique for FPGA-based aerospace applications | |
| type | Conference Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8195198 | |
| subject keywords | assembling | |
| subject keywords | n moulding | |
| subject keywords | n three-dimensional integrated circuits | |
| subject keywords | n wafer level packaging | |
| subject keywords | n 3D IC assembly process | |
| subject keywords | n CoW technology | |
| subject keywords | n SMC | |
| subject keywords | n WLP | |
| subject keywords | n chip thickness | |
| subject keywords | n chip-on-wafer technology | |
| subject keywords | n sheet-type molding compound | |
| subject keywords | n three-dimensional integrated circuit technology | |
| subject keywords | n ultra-thin chip stacking technology | |
| subject keywords | n wafer-level-packaging | |
| subject keywords | n Assembly | |
| subject keywords | n Bonding | |
| subject keywords | n Semiconductor device measurement | |
| subject keywords | n Silicon | |
| subject keywords | n Strain | |
| subject keywords | n Through-silicon vias | |
| subject keywords | n chip-on-wafer | |
| identifier doi | 10.1109/ICEP.2014.6826723 | |
| journal title | ormal Methods and Models for Codesign (MEMOCODE), 2014 Twelfth ACM/IEEE International Conference on | |
| filesize | 528274 | |
| citations | 0 |