Theoretical limitation of performance of decode-and-forward multinode cooperative communication systems with adaptive modulation scheme
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: 2014DOI: 10.1109/SPIN.2014.6776940
Keyword(s): VLSI,n computational complexity,n field programmable gate arrays,n hardware description languages,n image watermarking,n transforms,n FPGA,n HDL,n MSI number,n VLSI implementation,n Verilog HDL,n Walsh Transform,n computational complexity,n digital image watermarking,n field programmable gate array,n hardware architecture,n hardware description language synthesizer,n image authentication process,n image watermarking architecture,n real tim
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Theoretical limitation of performance of decode-and-forward multinode cooperative communication systems with adaptive modulation scheme
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| contributor author | Min-Kuany Chang | |
| contributor author | Shi-Yong Lee | |
| contributor author | Yu-Wei Chan | |
| contributor author | Yang, G.-C. | |
| date accessioned | 2020-03-12T21:34:37Z | |
| date available | 2020-03-12T21:34:37Z | |
| date issued | 2014 | |
| identifier other | 6947815.pdf | |
| identifier uri | http://libsearch.um.ac.ir:80/fum/handle/fum/1053368?locale-attribute=en | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | Theoretical limitation of performance of decode-and-forward multinode cooperative communication systems with adaptive modulation scheme | |
| type | Conference Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8183724 | |
| subject keywords | VLSI | |
| subject keywords | n computational complexity | |
| subject keywords | n field programmable gate arrays | |
| subject keywords | n hardware description languages | |
| subject keywords | n image watermarking | |
| subject keywords | n transforms | |
| subject keywords | n FPGA | |
| subject keywords | n HDL | |
| subject keywords | n MSI number | |
| subject keywords | n VLSI implementation | |
| subject keywords | n Verilog HDL | |
| subject keywords | n Walsh Transform | |
| subject keywords | n computational complexity | |
| subject keywords | n digital image watermarking | |
| subject keywords | n field programmable gate array | |
| subject keywords | n hardware architecture | |
| subject keywords | n hardware description language synthesizer | |
| subject keywords | n image authentication process | |
| subject keywords | n image watermarking architecture | |
| subject keywords | n real tim | |
| identifier doi | 10.1109/SPIN.2014.6776940 | |
| journal title | nformation Science, Electronics and Electrical Engineering (ISEEE), 2014 International Conference on | |
| filesize | 206009 | |
| citations | 0 |