A 0.18-μm CMOS fully integrated 0.7–6 GHz PLL-based complex dielectric spectroscopy system
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سال
: 2014شناسه الکترونیک: 10.1109/ISSCC.2014.6757414
کلیدواژه(گان): CMOS memory circuits,n MOSFET,n SRAM chips,n ARVDD,n DP-SRAM,n NMOS transistors,n SNM,n SP-SRAM,n SRAM cell transistors,n SRAM operation margin,n WL voltage level,n assist circuits,n degradation,n dual-port SRAM,n local variations,n negative BL techniques,n negative bitline techniques,n pass-gate NMOS,n process technology scaling,n pull-down NMOS,n pull-up PMOS,n read and write immunity,n read-assist approaches,n single-port SR
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A 0.18-μm CMOS fully integrated 0.7–6 GHz PLL-based complex dielectric spectroscopy system
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| contributor author | Elhadidy, O. | |
| contributor author | Shakib, S. | |
| contributor author | Krenek, K. | |
| contributor author | Palermo, S. | |
| contributor author | Entesari, K. | |
| date accessioned | 2020-03-12T21:31:31Z | |
| date available | 2020-03-12T21:31:31Z | |
| date issued | 2014 | |
| identifier other | 6945984.pdf | |
| identifier uri | http://libsearch.um.ac.ir:80/fum/handle/fum/1051612?locale-attribute=fa | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | A 0.18-μm CMOS fully integrated 0.7–6 GHz PLL-based complex dielectric spectroscopy system | |
| type | Conference Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8181676 | |
| subject keywords | CMOS memory circuits | |
| subject keywords | n MOSFET | |
| subject keywords | n SRAM chips | |
| subject keywords | n ARVDD | |
| subject keywords | n DP-SRAM | |
| subject keywords | n NMOS transistors | |
| subject keywords | n SNM | |
| subject keywords | n SP-SRAM | |
| subject keywords | n SRAM cell transistors | |
| subject keywords | n SRAM operation margin | |
| subject keywords | n WL voltage level | |
| subject keywords | n assist circuits | |
| subject keywords | n degradation | |
| subject keywords | n dual-port SRAM | |
| subject keywords | n local variations | |
| subject keywords | n negative BL techniques | |
| subject keywords | n negative bitline techniques | |
| subject keywords | n pass-gate NMOS | |
| subject keywords | n process technology scaling | |
| subject keywords | n pull-down NMOS | |
| subject keywords | n pull-up PMOS | |
| subject keywords | n read and write immunity | |
| subject keywords | n read-assist approaches | |
| subject keywords | n single-port SR | |
| identifier doi | 10.1109/ISSCC.2014.6757414 | |
| journal title | ustom Integrated Circuits Conference (CICC), 2014 IEEE Proceedings of the | |
| filesize | 691364 | |
| citations | 0 |