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FPGA acceleration of SAT/Max-SAT solving using variable-way cache

contributor authorKanazawa, K.
contributor authorMaruyama, T.
date accessioned2020-03-12T21:09:33Z
date available2020-03-12T21:09:33Z
date issued2014
identifier other6927405.pdf
identifier urihttp://libsearch.um.ac.ir:80/fum/handle/fum/1039027?locale-attribute=en&show=full
formatgeneral
languageEnglish
publisherIEEE
titleFPGA acceleration of SAT/Max-SAT solving using variable-way cache
typeConference Paper
contenttypeMetadata Only
identifier padid8165768
subject keywordsEducational institutions
subject keywordsElectromagnetic heating
subject keywordsElectronic mail
subject keywordsMicrowave technology
subject keywordsPhysics
subject keywordsResearch and development
subject keywordsThermal engineering
identifier doi10.1109/APEDE.2014.6958219
journal titleield Programmable Logic and Applications (FPL), 2014 24th International Conference on
filesize124723
citations0


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