High-speed pulsed-hysteresis-latch design for improved SER performance in 20 nm bulk CMOS process
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: 2014DOI: 10.1109/GHTC-SAS.2014.6967552
Keyword(s): Electricity,Government,Lighting,Production,Propagation losses,Renewable energy sources,Solar energy,photovoltaic solar home system,presizing,rural electrification,solar generation
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High-speed pulsed-hysteresis-latch design for improved SER performance in 20 nm bulk CMOS process
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| date accessioned | 2020-03-12T20:16:56Z | |
| date available | 2020-03-12T20:16:56Z | |
| date issued | 2014 | |
| identifier other | 6861095.pdf | |
| identifier uri | http://libsearch.um.ac.ir:80/fum/handle/fum/1008727?locale-attribute=en | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | High-speed pulsed-hysteresis-latch design for improved SER performance in 20 nm bulk CMOS process | |
| type | Conference Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8130651 | |
| subject keywords | Electricity | |
| subject keywords | Government | |
| subject keywords | Lighting | |
| subject keywords | Production | |
| subject keywords | Propagation losses | |
| subject keywords | Renewable energy sources | |
| subject keywords | Solar energy | |
| subject keywords | photovoltaic solar home system | |
| subject keywords | presizing | |
| subject keywords | rural electrification | |
| subject keywords | solar generation | |
| identifier doi | 10.1109/GHTC-SAS.2014.6967552 | |
| journal title | eliability Physics Symposium, 2014 IEEE International | |
| filesize | 332943 | |
| citations | 0 | |
| contributor rawauthor | Narasimham, B. , Chandrasekharan, K. , Wang, J.K. , Djaja, G. , Gaspard, N.J. , Mahatme, N.N. , Assis, T.R. , Bhuva, B.L. |