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نمایش تعداد 1-7 از 7

The design and implementation of heterogeneous multicore systems for energy-efficient speculative thread execution

نوع: Journal Paper

نویسنده : Yangchun Luo; Wei-Chung Hsu; Antonia Zhai

سال: 2013

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Runtime techniques for efficient Ray-Tracing on heterogeneous systems

نوع: Journal Paper

نویسنده : Chih-Chen Kao; Wei-Chung Hsu

سال: 2015

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Energy efficient speculative threads

نوع: Journal Paper

نویسنده : Yangchun Luo; Venkatesan Packirisamy; Wei-Chung Hsu; Antonia Zhai

سال: 2010

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HSAemu

نوع: Journal Paper

نویسنده : Jiun-Hung Ding; Wei-Chung Hsu; Bai-Cheng Jeng; Shih-Hao Hung; Yeh-Ching Chung

سال: 2014

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Dynamic performance tuning for speculative threads

نوع: Journal Paper

نویسنده : Yangchun Luo; Venkatesan Packirisamy; Wei-Chung Hsu; Antonia Zhai; Nikhil Mungre; Ankit Tarkas

سال: 2009

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Reducing Code Size by Graph Coloring Register Allocation and Assignment Algorithm for Mixed-Width ISA Processor

نوع: Journal Paper

نویسنده : Jyh-Shian Wang; I-Wei Wu; Yu-Sheng Chen; Jean Jyh-Jiun Shann; Wei-Chung Hsu

سال: 2009

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Efficient and Retargetable Dynamic Binary Translation on Multicores

نوع: Journal Paper

نویسنده : Ding-Yong Hong; Jan-Jan Wu; Pen-Chung Yew; Wei-Chung Hsu; Chun-Chen Hsu; Pangfeng Liu; Chien-Min Wang; Yeh-Ching Chung

ناشر: IEEE

سال: 2014

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The design and implementation of heterogeneous multicore systems for energy-efficient speculative thread execution

Runtime techniques for efficient Ray-Tracing on heterogeneous systems

Energy efficient speculative threads

HSAemu

Dynamic performance tuning for speculative threads

Reducing Code Size by Graph Coloring Register Allocation and Assignment Algorithm for Mixed-Width ISA Processor

Efficient and Retargetable Dynamic Binary Translation on Multicores

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The design and implementation of heterogeneous multicore systems for energy-efficient speculative thread execution

Runtime techniques for efficient Ray-Tracing on heterogeneous systems

Energy efficient speculative threads

HSAemu

Dynamic performance tuning for speculative threads

Reducing Code Size by Graph Coloring Register Allocation and Assignment Algorithm for Mixed-Width ISA Processor

Efficient and Retargetable Dynamic Binary Translation on Multicores