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نمایش تعداد 1-7 از 7

The Hamiltonian-based odd-even routing method for 3D Networks-on-Chip

نوع: Conference Paper

نویسنده : Bahrebar, Poona; Stroobandt, Dirk

ناشر: IEEE

سال: 2014

Characterizing Traffic Locality in 3D NoC-Based CMPs Using a Path-Based Partitioning Method

نوع: Conference Paper

نویسنده : Bahrebar, Poona; Stroobandt, Dirk

ناشر: IEEE

سال: 2014

Adaptive and reconfigurable fault-tolerant routing method for 2D Networks-on-Chip

نوع: Conference Paper

نویسنده : Bahrebar, Poona; Stroobandt, Dirk

ناشر: IEEE

سال: 2014

Data path analysis for dynamic circuit specialisation

نوع: Conference Paper

نویسنده : Davidson, Tom; Stroobandt, Dirk

ناشر: IEEE

سال: 2014

Parameterised FPGA reconfigurations for efficient test set generation

نوع: Conference Paper

نویسنده : Kourfali, Alexandra; Vansteenkiste, Elias; Stroobandt, Dirk

ناشر: IEEE

سال: 2014

TPaR: Place and Route Tools for the Dynamic Reconfiguration of the FPGA's Interconnect Network

نوع: Journal Paper

نویسنده : Vansteenkiste, Elias; Al Farisi, Brahim; Bruneel, Karel; Stroobandt, Dirk

ناشر: IEEE

سال: 2014

Improving reconfiguration speed for dynamic circuit specialization using placement constraints

نوع: Conference Paper

نویسنده : Kulkarni, Amit; Davidson, Tom; Heyse, Karel; Stroobandt, Dirk

ناشر: IEEE

سال: 2014

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The Hamiltonian-based odd-even routing method for 3D Networks-on-Chip

Characterizing Traffic Locality in 3D NoC-Based CMPs Using a Path-Based Partitioning Method

Adaptive and reconfigurable fault-tolerant routing method for 2D Networks-on-Chip

Data path analysis for dynamic circuit specialisation

Parameterised FPGA reconfigurations for efficient test set generation

TPaR: Place and Route Tools for the Dynamic Reconfiguration of the FPGA's Interconnect Network

Improving reconfiguration speed for dynamic circuit specialization using placement constraints

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The Hamiltonian-based odd-even routing method for 3D Networks-on-Chip

Characterizing Traffic Locality in 3D NoC-Based CMPs Using a Path-Based Partitioning Method

Adaptive and reconfigurable fault-tolerant routing method for 2D Networks-on-Chip

Data path analysis for dynamic circuit specialisation

Parameterised FPGA reconfigurations for efficient test set generation

TPaR: Place and Route Tools for the Dynamic Reconfiguration of the FPGA's Interconnect Network

Improving reconfiguration speed for dynamic circuit specialization using placement constraints