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In this paper, a low power SAR Analog to Digital Converter (ADC) with a resolution of 10 bits and a sampling rate of 4 to 32 MS/s is proposed. It utilizes an asynchronous process with an optimized D/A timing strategy to ...

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A 350-MS/s Continuous-Time Delta–Sigma Modulator With a Digitally Assisted Binary-DAC and a 5-Bits Two-Step-ADC Quantizer in 130-nm CMOS

Digital background calibration of a 0.4-pJ/step 10-bit pipelined ADC without PN generator in 90-nm digital CMOS

A 10-bit 110 kS/s 1.16 $\mu\hbox{W}$ SA-ADC With a Hybrid Differential/Single-Ended DAC in 180-nm CMOS for Multichannel Biomedical Applications

A 1-V 690 μW 8-bit 200 MS/s flash-SAR ADC with pipelined operation of flash and SAR ADCs in 0.13μm CMOS

A 10-Gb/s low-power low-voltage CTLE using gate and bulk driven transistors

65 nm CMOS switching discontinuous-conduction mode buck converter with 330 ns start-up time for light-load power-cycled applications

A low-power design methodology for high-resolution pipelined analog-to-digital converters

Low-power design techniques for low-voltage fast-settling operational amplifiers in switched-capacitor applications

Reduced-sized voltage-mode driver for high-speed I/O utilizing dynamic current-driven bulk biasing

A 5.3-9.3 fJ/Conversion-Step 4-32 MS/s 10 bit Asynchronous SAR ADC with Optimized DAC Timing Strategy in 0.13 µm CMOS

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A 350-MS/s Continuous-Time Delta–Sigma Modulator With a Digitally Assisted Binary-DAC and a 5-Bits Two-Step-ADC Quantizer in 130-nm CMOS

Digital background calibration of a 0.4-pJ/step 10-bit pipelined ADC without PN generator in 90-nm digital CMOS

A 10-bit 110 kS/s 1.16 $\mu\hbox{W}$ SA-ADC With a Hybrid Differential/Single-Ended DAC in 180-nm CMOS for Multichannel Biomedical Applications

A 1-V 690 μW 8-bit 200 MS/s flash-SAR ADC with pipelined operation of flash and SAR ADCs in 0.13μm CMOS

A 10-Gb/s low-power low-voltage CTLE using gate and bulk driven transistors

65 nm CMOS switching discontinuous-conduction mode buck converter with 330 ns start-up time for light-load power-cycled applications

A low-power design methodology for high-resolution pipelined analog-to-digital converters

Low-power design techniques for low-voltage fast-settling operational amplifiers in switched-capacitor applications

Reduced-sized voltage-mode driver for high-speed I/O utilizing dynamic current-driven bulk biasing

A 5.3-9.3 fJ/Conversion-Step 4-32 MS/s 10 bit Asynchronous SAR ADC with Optimized DAC Timing Strategy in 0.13 µm CMOS