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Author : Yuan Du; Wei-Han Cho; Po-Tsang Huang; Yilei Li; Chien-Heng Wong; Jieqiong Du; Yanghyo Kim; Boyu Hu; Li Du; Chunchen Liu; Sheau Jiung Lee; Mau-Chung Frank Chang

Year: 2017

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40-Gb/s 0.7-V 2:1 MUX and 1:2 DEMUX with Transformer-Coupled Technique for SerDes Interface

A 65 nm CMOS 330 Mb/s Microwave Backscatter Link at 2.4 to 2.9 GHz With Ambient Blocker Cancellation

An architecture-reconfigurable 3b-to-7b 4GS/s-to-1.5GS/s ADC using subtractor interleaving

Wireless Gigabit Data Telemetry for Large-Scale Neural Recording

DPLL for Phase Noise Cancellation in Ring Oscillator-Based Quadrature Receivers

A 10-Gb/s Low Jitter Single-Loop Clock and Data Recovery Circuit With Rotational Phase Frequency Detector

A 16-Gb/s 14.7-mW Tri-Band Cognitive Serial Link Transmitter With Forwarded Clock to Enable PAM-16/256-QAM and Channel Response Detection

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40-Gb/s 0.7-V 2:1 MUX and 1:2 DEMUX with Transformer-Coupled Technique for SerDes Interface

A 65 nm CMOS 330 Mb/s Microwave Backscatter Link at 2.4 to 2.9 GHz With Ambient Blocker Cancellation

An architecture-reconfigurable 3b-to-7b 4GS/s-to-1.5GS/s ADC using subtractor interleaving

Wireless Gigabit Data Telemetry for Large-Scale Neural Recording

DPLL for Phase Noise Cancellation in Ring Oscillator-Based Quadrature Receivers

A 10-Gb/s Low Jitter Single-Loop Clock and Data Recovery Circuit With Rotational Phase Frequency Detector

A 16-Gb/s 14.7-mW Tri-Band Cognitive Serial Link Transmitter With Forwarded Clock to Enable PAM-16/256-QAM and Channel Response Detection