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نمایش تعداد 1-10 از 21

Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors

نوع: Journal Paper

نویسنده : Khan, O.; Kundu, S.

سال: 2010

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A generic and efficient modeling of phase margin of high performance CMOS OpAmps

نوع: Conference Paper

نویسنده : Kundu, S. , Mandal, P.

ناشر: IEEE

سال: 2014

A modified BP network using malsburg learning for rotation and location invariant fingerprint recognition and localization with and without occlusion

نوع: Conference Paper

نویسنده : Kundu, S. , Sarker, G.

ناشر: IEEE

سال: 2014

Network-on-Chip Design for Heterogeneous Multiprocessor System-on-Chip

نوع: Conference Paper

نویسنده : Phanibhushana, B. , Kundu, S.

ناشر: IEEE

سال: 2014

Glitch Power Reduction via Clock Skew Scheduling

نوع: Conference Paper

نویسنده : Vijayakumar, A. , Kundu, S.

ناشر: IEEE

سال: 2014

Performance and Power Benefits of Sharing Execution Units between a High Performance Core and a Low Power Core

نوع: Conference Paper

نویسنده : Rodrigues, R. , Koren, I. , Kundu, S.

سال: 2014

On Manufacturing Aware Physical Design to Improve the Uniqueness of Silicon-Based Physically Unclonable Functions

نوع: Conference Paper

نویسنده : Kumar, R. , Dhanuskodi, S.N. , Kundu, S.

سال: 2014

Outage and SEP of secondary user with imperfect channel estimation and primary user interference

نوع: Conference Paper

نویسنده : Prasad, B. , Roy, S.D. , Kundu, S.

سال: 2014

Gain and SAR improvement of a conventional patch antenna using a novel Pi-shaped DNG metamaterial

نوع: Conference Paper

نویسنده : Mallik, A. , Kundu, S. , Goni, M.O.

ناشر: IEEE

سال: 2014

Small monopole antenna with corner modified patch for UWB applications

نوع: Conference Paper

نویسنده : Kundu, S. , Kundu, M. , Mandal, K.

ناشر: IEEE

سال: 2014

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Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors

A generic and efficient modeling of phase margin of high performance CMOS OpAmps

A modified BP network using malsburg learning for rotation and location invariant fingerprint recognition and localization with and without occlusion

Network-on-Chip Design for Heterogeneous Multiprocessor System-on-Chip

Glitch Power Reduction via Clock Skew Scheduling

Performance and Power Benefits of Sharing Execution Units between a High Performance Core and a Low Power Core

On Manufacturing Aware Physical Design to Improve the Uniqueness of Silicon-Based Physically Unclonable Functions

Outage and SEP of secondary user with imperfect channel estimation and primary user interference

Gain and SAR improvement of a conventional patch antenna using a novel Pi-shaped DNG metamaterial

Small monopole antenna with corner modified patch for UWB applications

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Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors

A generic and efficient modeling of phase margin of high performance CMOS OpAmps

A modified BP network using malsburg learning for rotation and location invariant fingerprint recognition and localization with and without occlusion

Network-on-Chip Design for Heterogeneous Multiprocessor System-on-Chip

Glitch Power Reduction via Clock Skew Scheduling

Performance and Power Benefits of Sharing Execution Units between a High Performance Core and a Low Power Core

On Manufacturing Aware Physical Design to Improve the Uniqueness of Silicon-Based Physically Unclonable Functions

Outage and SEP of secondary user with imperfect channel estimation and primary user interference

Gain and SAR improvement of a conventional patch antenna using a novel Pi-shaped DNG metamaterial

Small monopole antenna with corner modified patch for UWB applications