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Now showing items 1-7 of 7
AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture
Publisher: IEEE
Year: 2014
Printed Low-Voltage Fuse Memory on Paper
Publisher: IEEE
Year: 2014
Experimental investigation of signal time misalignment in dynamic load modulation amplifiers
Publisher: IEEE
Year: 2014
High Sum-Rate Three-Write and Nonbinary WOM Codes
Publisher: IEEE
Year: 2014
Multi sensor underwater pipeline tracking with AUVs
Publisher: IEEE
Year: 2014
Fault current analysis of DC electric railway feeding systems using superconducting power cables
Publisher: IEEE
Year: 2014
Experimental performance analysis of two-hop aerial 802.11 networks
Publisher: IEEE
Year: 2014