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Time-to-Digital Converter Based on FPGA With Multiple Channel Capability

Type: Journal Paper

Author : Torres, Juana; Aguilar, Albert; Garcia-Olcina, R.; Martinez, Philip /A/.; Martos, J.; Soret, J.; Benlloch, J.M.; Conde, P.; Gonzalez, A.J.; Sanchez, F.

Publisher: IEEE

Year: 2014

Operating Systems Research for Reconfigurable Computing

Type: Journal Paper

Author : Andrews, D.

Publisher: IEEE

Year: 2014

<inline-formula> <img src="/images/tex/21736.gif" alt="(M,p,k)"> </inline-formula>-Friendly Points: A Table-Based Method to Evaluate Trigonometric Function

Type: Journal Paper

Author : Dong Wang; Muller, J.-M.; Brisebarre, N.; Ercegovac, Milos D.

Publisher: IEEE

Year: 2014

Precise VLSI Architecture for AI Based 1-D/ 2-D Daub-6 Wavelet Filter Banks With Low Adder-Count

Type: Journal Paper

Author : Madishetty, Shiva K.; Madanayake, A.; Cintra, Renato J.; Dimitrov, Vassil S.

Publisher: IEEE

Year: 2014

Software/Hardware Parallel Long-Period Random Number Generation Framework Based on the WELL Method

Type: Journal Paper

Author : Yuan Li; Chow, Peter; Jiang Jiang; Minxuan Zhang; Shaojun Wei

Publisher: IEEE

Year: 2014

Real-Time Machine Vision FPGA Implementation for Microfluidic Monitoring on Lab-on-Chips

Type: Journal Paper

Author : Sotiropoulou, C.-L.; Voudouris, Liberis; Gentsos, Christos; Demiris, Athanasios M.; Vassiliadis, Nikolaos; Nikolaidis, S.

Publisher: IEEE

Year: 2014

ASIC implementation of physical downlink shared channel for LTE

Type: Conference Paper

Author : Digish, K.G.; Thilagavathy, R.

Publisher: IEEE

Year: 2014

S4-P7: Low-temperature hydrophobic wafer bonding for 1200V, 25A bi-directional Si UMOS IGBTs

Type: Conference Paper

Author : Wu, J-W.; Chowdhury, S.; Naik, H.; Picard, J.; Lee, N.; Hitchcock, C.; Lu, J.J.-Q.; Chow, T.P.

Publisher: IEEE

Year: 2014

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Time-to-Digital Converter Based on FPGA With Multiple Channel Capability

Operating Systems Research for Reconfigurable Computing

<inline-formula> <img src="/images/tex/21736.gif" alt="(M,p,k)"> </inline-formula>-Friendly Points: A Table-Based Method to Evaluate Trigonometric Function

Precise VLSI Architecture for AI Based 1-D/ 2-D Daub-6 Wavelet Filter Banks With Low Adder-Count

Software/Hardware Parallel Long-Period Random Number Generation Framework Based on the WELL Method

Real-Time Machine Vision FPGA Implementation for Microfluidic Monitoring on Lab-on-Chips

ASIC implementation of physical downlink shared channel for LTE

S4-P7: Low-temperature hydrophobic wafer bonding for 1200V, 25A bi-directional Si UMOS IGBTs

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Time-to-Digital Converter Based on FPGA With Multiple Channel Capability

Operating Systems Research for Reconfigurable Computing

<inline-formula> <img src="/images/tex/21736.gif" alt="(M,p,k)"> </inline-formula>-Friendly Points: A Table-Based Method to Evaluate Trigonometric Function

Precise VLSI Architecture for AI Based 1-D/ 2-D Daub-6 Wavelet Filter Banks With Low Adder-Count

Software/Hardware Parallel Long-Period Random Number Generation Framework Based on the WELL Method

Real-Time Machine Vision FPGA Implementation for Microfluidic Monitoring on Lab-on-Chips

ASIC implementation of physical downlink shared channel for LTE

S4-P7: Low-temperature hydrophobic wafer bonding for 1200V, 25A bi-directional Si UMOS IGBTs