A power-efficient successive approximation analogue-to-digital converter (SA-ADC) is proposed. In order to reduce the energy consumption of the employed capacitive digital-to-analogue converter (DAC), a new low-energy ...

This paper presents a modified structure and a new switching algorithm in successive-approximation analog-to-digital converters to reduce the power consumption. This technique is more efficient in applications where the ...

A new switching algorithm is proposed in Successive Approximation Analog-to-Digital Converters (SA-ADCs) to reduce the power consumption in both DAC and comparator. This technique is more efficient in applications where ...

In this paper a new architecture for successive approximation analog-to-digital converters (SAR-ADCs) using generalized non-binary search algorithm is proposed to reduce the complexity and the power consumption overhead ...

This paper presents a modified structure and a new switching algorithm in successive-approximation analog-to-digital converters to reduce the power consumption. This technique is more efficient in applications where the ...

Successive-approximation analog-to-digital converters (SA-ADCs) are widely used in ultra-low-power applications. In this paper, the power consumption and the linearity of capacitive-array digital-to-analog converters (DACs) ...

In this paper, a new low-energy switching technique with low common-mode voltage variation is proposed for successive-approximation analog-to-digital converters (SA-ADCs). In the proposed scheme, not only the switching ...

This paper presents a new sampling technique and a successive approximation analog to digital converter

(SA-ADC) which samples sparse signals in a non-uniform adaptive way. The proposed sampling technique has the ...

In this paper, the structure of a binary-weighted capacitive digital-to-analog converter (DAC) in a successive-approximation analog-to-digital converter (SA-ADC) is modified to a unary or segmented configuration to reduce ...