Multitude parameters in the design process of a reconfigurable instruction-set processor (RISP) may lead to a large design space and remarkable complexity. Quantitative design approach uses the data collected from applications to satisfy design...

Performance evaluation is a serious challenge in

designing or optimizing reconfigurable instruction set processors.

The conventional approaches based on synthesis and simulations

are very time consuming and need a considerable...

This paper introduces an energy efficient acceleration

technique for embedded microprocessors. By means of

supporting an ALU-array based coarse-grain reconfigurable

functional unit, well customized special instructions...

Runtime reconfiguration is a fundamental requirement of many telecommunication applications which also has been addressed by management standards like CMIP, 3GPP TS 32.602, and NETCONF. Two basic commands considered by these standards are CREATE...

This paper presents a mixed-signal hybrid CMOS/Nano circuit to implement a fully programmable fuzzy processor that performs the zero-order Sugeno's algorithm. The programmability is incorporated in both the rule base and ...

A configurable terahertz (THz) graphene-based metamaterial absorber is designed in this paper.
Taking advantage of dual bias graphene ribbons and disks with a golden plate, the reconfigurable
absorber achieves absorption over 90% in three...

Power analysis based side channel attacks are

significant security risk in embedded applications.

Reconfigurable architecture has already been proposed as a

security improvement method for run time monitoring systems...