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A high parallel way for processing IQ/IT part of HEVC decoder based on GPU

نوع: Conference Paper

نویسنده : He, Lang-ping; Goto, Satoshi

ناشر: IEEE

سال: 2014

[IEEE 2012 IEEE International Conference on Multimedia and Expo (ICME) - Melbourne, Australia (2012.07.9-2012.07.13)] 2012 IEEE International Conference on Multimedia and Expo - A Low-Complexity HEVC Intra Prediction Algorithm Based on Level and Mode Filtering

نوع: Journal Paper

نویسنده : Sun, Heming; Zhou, Dajiang; Goto, Satoshi

سال: 2012

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OpenCL based high-quality HEVC motion estimation on GPU

نوع: Conference Paper

نویسنده : Wang, Fan; Zhou, Dajiang; Goto, Satoshi

ناشر: IEEE

سال: 2014

Non-Redundant Gradient Semantic Local Binary Patterns for pedestrian detection

نوع: Conference Paper

نویسنده : Xu, Jiu; Jiang, Ning; Goto, Satoshi

ناشر: IEEE

سال: 2014

Live demonstration: FPGA based 3840×2160 video decoding and displaying system

نوع: Conference Paper

نویسنده : Zhang, Haoming; Zhou, Dajiang; Goto, Satoshi

ناشر: IEEE

سال: 2014

A New Reference Frame Recompression Algorithm and Its VLSI Architecture for UHDTV Video Codec

نوع: Journal Paper

نویسنده : Li Guo; Dajiang Zhou; Goto, Satoshi

ناشر: IEEE

سال: 2014

A 1.59 Gpixel/s Motion Estimation Processor With <formula formulatype="inline"> <img src="/images/tex/277.gif" alt="-"> </formula>211 to +211 Search Range for UHDTV Video Encoder

نوع: Journal Paper

نویسنده : Dajiang Zhou; Jinjia Zhou; Gang He; Goto, Satoshi

ناشر: IEEE

سال: 2014

A low power 720p motion estimation processor with 3D stacked memory

نوع: Conference Paper

نویسنده : Zhang, Shuping; Zhou, Jinjia; Zhou, Dajiang; Goto, Satoshi

ناشر: IEEE

سال: 2014

Reducing power consumption of HEVC codec with lossless reference frame recompression

نوع: Conference Paper

نویسنده : Zhou, Dajiang; Guo, Li; Zhou, Jinjia; Goto, Satoshi

ناشر: IEEE

سال: 2014

VLSI architecture of HEVC intra prediction for 8K UHDTV applications

نوع: Conference Paper

نویسنده : Zhou, Jianbin; Zhou, Dajiang; Sun, Heming; Goto, Satoshi

ناشر: IEEE

سال: 2014

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A high parallel way for processing IQ/IT part of HEVC decoder based on GPU

[IEEE 2012 IEEE International Conference on Multimedia and Expo (ICME) - Melbourne, Australia (2012.07.9-2012.07.13)] 2012 IEEE International Conference on Multimedia and Expo - A Low-Complexity HEVC Intra Prediction Algorithm Based on Level and Mode Filtering

OpenCL based high-quality HEVC motion estimation on GPU

Non-Redundant Gradient Semantic Local Binary Patterns for pedestrian detection

Live demonstration: FPGA based 3840×2160 video decoding and displaying system

A New Reference Frame Recompression Algorithm and Its VLSI Architecture for UHDTV Video Codec

A 1.59 Gpixel/s Motion Estimation Processor With <formula formulatype="inline"> <img src="/images/tex/277.gif" alt="-"> </formula>211 to +211 Search Range for UHDTV Video Encoder

A low power 720p motion estimation processor with 3D stacked memory

Reducing power consumption of HEVC codec with lossless reference frame recompression

VLSI architecture of HEVC intra prediction for 8K UHDTV applications

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A high parallel way for processing IQ/IT part of HEVC decoder based on GPU

[IEEE 2012 IEEE International Conference on Multimedia and Expo (ICME) - Melbourne, Australia (2012.07.9-2012.07.13)] 2012 IEEE International Conference on Multimedia and Expo - A Low-Complexity HEVC Intra Prediction Algorithm Based on Level and Mode Filtering

OpenCL based high-quality HEVC motion estimation on GPU

Non-Redundant Gradient Semantic Local Binary Patterns for pedestrian detection

Live demonstration: FPGA based 3840&#x00D7;2160 video decoding and displaying system

A New Reference Frame Recompression Algorithm and Its VLSI Architecture for UHDTV Video Codec

A 1.59 Gpixel/s Motion Estimation Processor With <formula formulatype="inline"> <img src="/images/tex/277.gif" alt="-"> </formula>211 to +211 Search Range for UHDTV Video Encoder

A low power 720p motion estimation processor with 3D stacked memory

Reducing power consumption of HEVC codec with lossless reference frame recompression

VLSI architecture of HEVC intra prediction for 8K UHDTV applications

Live demonstration: FPGA based 3840×2160 video decoding and displaying system