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RISA 350-MS/s Continuous-Time Delta–Sigma Modulator With a Digitally Assisted Binary-DAC and a 5-Bits Two-Step-ADC Quantizer in 130-nm CMOS
Two techniques to improve the performance of continuous-time delta–sigma (CTDS) modulators are presented. A digital calibration technique is introduced to enable the use of binary current digital-to-analog converters (DACs) ...
A Switching Buck Converter with Dual Loop Controller and Segmented Output Stage with Improved Start-up and Transient Response
In this paper, a method is presented to improve the
transient response of a buck converter. This method is based on
using dual-loop voltage-mode controller along with a segmented
power transistor stage. ...
Digital Background Calibration of Capacitor Mismatch Errors in Pipelined ADCs
A digital background calibration technique is proposed to correct for the linearity error due to capacitor mismatches in pipelined analog-to-digital converters (ADCs). During the normal ADC operation, it randomly swaps the ...
Area and Power Optimization of High-Order Gain Calibration in Digitally-Enhanced Pipelined ADCs
Digital calibration techniques are widely utilized to linearize pipelined analog-to-digital converters (ADCs). However, their power dissipation can be prohibitively high, particularly when high-order gain calibration is ...
A Reconfigurable and Power-Scalable 10-12 bit 0.4-44 MS/s Pipelined ADC with 0.35-0.5 pJ/step in 1.2 V 90 nm Digital CMOS
A pipelined ADC, reconfigurable over bandwidths of 0.2-22 MHz (sampling frequencies of 0.4-44 MS/s) and resolutions of 10-12 bits, is described for applications in multi-standard wireless terminals. Fabricated in a 1.2-V ...
A 1-V Process-Insensitive Current-Scalable Two-Stage Opamp with Enhanced DC Gain and Settling Behavior in 65-nm Digital CMOS
A pseudo-cascode compensation technique is proposed to enable a process-insensitive and current-scalable design of the classical two-stage opamp at low supply voltages, without requiring any additional power dissipation. ...
A 10-bit 110 kS/s 1.16 μW SA-ADC With a Hybrid Differential/Single-Ended DAC in 180-nm CMOS for Multichannel Biomedical Applications
A 10-bit 110-kS/s successive-approximation analog to digital converter (ADC) for multichannel biomedical applications is presented. In order to achieve low-power operation, the ADC utilizes a reduced-speed dynamic comparator, ...
A Highly Efficient and Linear Broadband Common-Drain CMOS Power Amplifier With Transformer-Based Input-Matching Network
A broadband common-drain power amplifier (PA) with a transformer-based input matching network that is implemented in a 0.13 m CMOS process is presented. This structure provides sufficient power gain along with high linearity ...
65 nm CMOS switching discontinuous conduction mode buck converter with 330 ns start-up time for light-load power-cycled applications
Aggressive power cycling of DC-DC converters is becoming important in many applications ranging from sensor interfaces to wireless transceivers, where the system needs to be on for only short time intervals. In this study, ...
An 80%-Efficiency Switched-Capacitor Step-Down DC-DC Converter with Switch-Width and Digital Capacitance Modulation
This paper presents a switched-capacitor stepdown
DC-DC converter using switch-width modulation (SWM)
and digital capacitance modulation (DCM), to maintain the
converter efficiency for various load ...