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Now showing items 1-6 of 6

Exploring potentials of perpendicular magnetic anisotropy STT-MRAM for cache design

Type: Conference Paper

Author : Xiaolong Zhang; Yuanqing Cheng; Weisheng Zhao; Youguang Zhang; Todri-Sanial, A.

Publisher: IEEE

Year: 2014

Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach

Type: Journal Paper

Author : Jianlei Yang; Peiyuan Wang; Yaojun Zhang; Yuanqing Cheng; Weisheng Zhao; Yiran Chen; Hai Li

Year: 2015

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Channel Modeling and Reliability Enhancement Design Techniques for STT-MRAM

Type: Journal Paper

Author : Liuyang Zhang; Wang Kang; Youguang Zhang; Yuanqing Cheng; Lang Zeng; Jacques-Olivier Klein; Weisheng Zhao

Year: 2015

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A novel SEU-tolerant MRAM latch circuit based on C-element

Type: Conference Paper

Author : Deming Zhang; Wang Kang; Yuanqing Cheng; Geifei Wang; Ravelosona, D.; Youguang Zhang; Klein, J.-O.; Weisheng Zhao

Publisher: IEEE

Year: 2014

A dynamic reference scheme to improve the sensing reliability of magnetic random access memory

Type: Conference Paper

Author : Wang Kang; Zheng Li; Yuanqing Cheng; Klein, J.-O.; Youguang Zhang; Ravelosona, D.; Chappert, C.; Weisheng Zhao

Publisher: IEEE

Year: 2014

Compact Model of Subvolume MTJ and Its Design Application at Nanoscale Technology Nodes

Type: Journal Paper

Author : Yue Zhang; Bonan Yan; Wang Kang; Yuanqing Cheng; Jacques-Olivier Klein; Youguang Zhang; Yiran Chen; Weisheng Zhao

Year: 2015

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Exploring potentials of perpendicular magnetic anisotropy STT-MRAM for cache design

Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach

Channel Modeling and Reliability Enhancement Design Techniques for STT-MRAM

A novel SEU-tolerant MRAM latch circuit based on C-element

A dynamic reference scheme to improve the sensing reliability of magnetic random access memory

Compact Model of Subvolume MTJ and Its Design Application at Nanoscale Technology Nodes

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Exploring potentials of perpendicular magnetic anisotropy STT-MRAM for cache design

Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach

Channel Modeling and Reliability Enhancement Design Techniques for STT-MRAM

A novel SEU-tolerant MRAM latch circuit based on C-element

A dynamic reference scheme to improve the sensing reliability of magnetic random access memory

Compact Model of Subvolume MTJ and Its Design Application at Nanoscale Technology Nodes