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An 8-GHz to 10-GHz Distributed DLL for Multiphase Clock Generation

Type: Journal Paper

Author : Tai-Cheng Lee; Keng-Jan Hsiao

Publisher: IEEE

Year: 2009

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A 6-b 1.3Gs/s A/D Converter with C-2C Switch-Capacitor Technique

Type: Journal Paper

Author : Ying-min Liao; Tai-cheng Lee

Year: 2006

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2.4-GHz High-Efficiency Adaptive Power

Type: Journal Paper

Author : Cheng-Jyun Li; Tai-Cheng Lee

Publisher: IEEE

Year: 2014

A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique

Type: Conference Paper

Author : Chin-Yu Lin , Tai-Cheng Lee

Publisher: IEEE

Year: 2014

A 3X-oversampling hybrid clock and data recovery circuit with programmable bandwidth

Type: Conference Paper

Author : Jia-An Jheng , Wei-Sung Chang , Tai-Cheng Lee

Publisher: IEEE

Year: 2014

A 20-MHz BW 75-dB SFDR shifted-averaging VCO-based ΔΣ modulator

Type: Conference Paper

Author : Yu-Hsuan Kang , Chin-Yu Lin , Tai-Cheng Lee

Publisher: IEEE

Year: 2014

A Fractional-N Divider-Less Phase-Locked Loop With a Subsampling Phase Detector

Type: Journal Paper

Author : Wei-Sung Chang; Po-Chun Huang; Tai-Cheng Lee

Publisher: IEEE

Year: 2014

A 200-MS/s Phase-Detector-Based Comparator With 400- $\\mu\\text{V}_{\\mathrm{rms}}$ Noise

Type: Journal Paper

Author : Chin-Yu Lin; Chien-Heng Wong; Chia-Hau Hsu; Yen-Hsin Wei; Tai-Cheng Lee

Year: 2016

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An 8-GHz to 10-GHz Distributed DLL for Multiphase Clock Generation

A 6-b 1.3Gs/s A/D Converter with C-2C Switch-Capacitor Technique

2.4-GHz High-Efficiency Adaptive Power

A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique

A 3X-oversampling hybrid clock and data recovery circuit with programmable bandwidth

A 20-MHz BW 75-dB SFDR shifted-averaging VCO-based ΔΣ modulator

A Fractional-N Divider-Less Phase-Locked Loop With a Subsampling Phase Detector

A 200-MS/s Phase-Detector-Based Comparator With 400- $\\mu\\text{V}_{\\mathrm{rms}}$ Noise

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An 8-GHz to 10-GHz Distributed DLL for Multiphase Clock Generation

A 6-b 1.3Gs/s A/D Converter with C-2C Switch-Capacitor Technique

2.4-GHz High-Efficiency Adaptive Power

A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique

A 3X-oversampling hybrid clock and data recovery circuit with programmable bandwidth

A 20-MHz BW 75-dB SFDR shifted-averaging VCO-based &#x0394;&#x03A3; modulator

A Fractional-N Divider-Less Phase-Locked Loop With a Subsampling Phase Detector

A 200-MS/s Phase-Detector-Based Comparator With 400- $\\mu\\text{V}_{\\mathrm{rms}}$ Noise

A 20-MHz BW 75-dB SFDR shifted-averaging VCO-based ΔΣ modulator