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RISScenario-based quasi-static task mapping and scheduling for temperature-efficient MPSoC design under process variation
Nowadays, employing the worst case analysis is the most common approach to provide unified static task mapping–scheduling plans on MPSoCs. Since the whole design space nor a subset of design space are not explored in the ...
Critical path-aware voltage island partitioning and floorplanning for hard real-time embedded systems
Temperature and power are two major issues for multiple supply voltage (MSV)-aware embedded systems that due to their different physical behavior are required to be considered to gether in the system design especially in ...
Proportionally-Fair Best Effort Flow Control in Network-on-Chip Architectures
The research community has recently witnessed the
emergence of Multi-Processor System on Chip
(MPSoC) platforms consisting of a large set of
embedded processors. Particularly, Interconnect
networks ...
A Novel Congestion Control Scheme in Network-on-Chip Based on Best Effort Delay-Sum Optimization
With the advances of the semiconductor technology,
the enormous number of transistors available on a
single chip allows designers to integrate dozens of IP
blocks together with large amounts of ...
Proportionally fair flow control mechanism for best effort traffic in network-on-chip architectures
The research community has recently witnessed the emergence of multi-processor
system on chip (MPSoC) platforms consisting of a large set of embedded processors.
Particularly, Interconnect networks methodology ...