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Now showing items 1-10 of 52

Variation-Aware Variable Latency Design

Type: Journal Paper

Author : Gupta, Swastik; Sapatnekar, Sachin S.

Publisher: IEEE

Year: 2014

A Supply-Noise Sensitivity Tracking PLL in 32 nm SOI Featuring a Deep Trench Capacitor Based Loop Filter

Type: Journal Paper

Author : Bongjin Kim; Weichao Xu; Kim, Chul Han

Publisher: IEEE

Year: 2014

Variability Modeling and Process Optimization for the 32 nm BEOL Using In-Line Scatterometry Data

Type: Journal Paper

Author : Faruk, M. Golam; Angyal, Matthew S.; Ogunsola, Oluwafemi; Watts, David K.; Wilkins, Richard

Publisher: IEEE

Year: 2014

Constraint-based platform variants specification for early system verification

Type: Conference Paper

Publisher: IEEE

Year: 2014

Optimal dimensioning of active cell balancing architectures

Type: Conference Paper

Publisher: IEEE

Year: 2014

An efficient reliable PUF-based cryptographic key generator in 65nm CMOS

Type: Conference Paper

Author : Bhargava, M. , Mai, K.

Publisher: IEEE

Year: 2014

Application of optimization method for optimal control of the steelmaking process

Type: Conference Paper

Author : Laciak, M. , Kacur, J. , Durdan, M. , Flegner, P.

Publisher: IEEE

Year: 2014

Design and Analysis of Single-Event Tolerant Slave Latches for Enhanced Scan Delay Testing

Type: Journal Paper

Author : Yang Lu; Lombardi, Floriana; Pontarelli, Salvatore; Ottavi, Marco

Publisher: IEEE

Year: 2014

Measuring propagation delays of critical paths using time-resolved LADA

Type: Conference Paper

Publisher: IEEE

Year: 2014

A Dynamic User Interface for Transit Tracking Applications

Type: Conference Paper

Author : Gelowitz, Craig M. , Paranjape, Raman

Publisher: IEEE

Year: 2014

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Variation-Aware Variable Latency Design

A Supply-Noise Sensitivity Tracking PLL in 32 nm SOI Featuring a Deep Trench Capacitor Based Loop Filter

Variability Modeling and Process Optimization for the 32 nm BEOL Using In-Line Scatterometry Data

Constraint-based platform variants specification for early system verification

Optimal dimensioning of active cell balancing architectures

An efficient reliable PUF-based cryptographic key generator in 65nm CMOS

Application of optimization method for optimal control of the steelmaking process

Design and Analysis of Single-Event Tolerant Slave Latches for Enhanced Scan Delay Testing

Measuring propagation delays of critical paths using time-resolved LADA

A Dynamic User Interface for Transit Tracking Applications

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Variation-Aware Variable Latency Design

A Supply-Noise Sensitivity Tracking PLL in 32 nm SOI Featuring a Deep Trench Capacitor Based Loop Filter

Variability Modeling and Process Optimization for the 32 nm BEOL Using In-Line Scatterometry Data

Constraint-based platform variants specification for early system verification

Optimal dimensioning of active cell balancing architectures

An efficient reliable PUF-based cryptographic key generator in 65nm CMOS

Application of optimization method for optimal control of the steelmaking process

Design and Analysis of Single-Event Tolerant Slave Latches for Enhanced Scan Delay Testing

Measuring propagation delays of critical paths using time-resolved LADA

A Dynamic User Interface for Transit Tracking Applications