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The Performance of a Classifier by Testing Only the Significant Events
Publisher: IEEE
Year: 2014
Implementing a High Throughput, Configurable and Parameterizable Packet Filtering Firewall on FPGA
Year: 2015
Abstract:
Array (FPGA). The firewall takes advantage of Ternary Content Addressable Memories (TCAMs) to store rule tables. Two different methods to update the firewall rules in TCAM modules are presented and verified. The proposed firewall system achieves...
FPGA Implementation of a Short Read Mapping Accelerator
Year: 2017
Abstract:
accelerate short read alignment being prototyped on an FPGA. We use a seed
and compare architecture based on FM-index method. Also pre-calculated data
are used for more performance improvement. A multi-core accelerator based on
the proposed...