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Domino ADC: A novel analog-to-digital converter architecture
A novel analog-to-digital converter (ADC)
architecture, named domino architecture, is introduced. The
proposed idea can be taken as the continuous-time counterpart
of SAR ADCs, and at the same time it resembles a series version...
Successive Approximation ADC with Redundancy Using Split Capacitive-Array DAC
In this paper a new architecture for successive approximation analog-to-digital converters (SAR-ADCs) using generalized non-binary search algorithm is proposed to reduce the complexity and the power consumption overhead of the digital circuitry...
A Signal-Specific Successive-Approximation Analog-to-Digital Converter
and with the proposed structure, the simulated power consumption of the DAC, the comparator and the entire ADC for an 8-bit 1-kS/s converter are 75%, 43% and 50% smaller than those of a conventional architecture, respectively....
A low-power architecture for integrating analog-to-digital converters
This paper reports on a modified architecture for
single-slope integrating analog-to-digital converter (ADC) for
use in image sensors and biomedical or any other applications
where the value of the input analog signal has small...
A Fully-Synchronous Offset-Insensitive Level-Crossing Analog-to-Digital Converter
A fully-synchronous offset-insensitive structure is proposed for implementing level-crossing analog-to-digital converters (LC-ADCs). The proposed structure is designed and implemented for high-precision compressed electrocardiogram (ECG) monitoring...
A 1-V 690 µW 8-bit 200 MS/s Flash-SAR ADC with Pipelined Operation of Flash and SAR ADCs in 0.13µm CMOS
The successive-approximation-register (SAR) analog-to-digital converter (ADC) has recently attracted a
lot of interest due to its power efficiency as well as its simple structure. The main challenge with this type of ADC is the limited...